1. Field of the Invention
The present invention relates to a wiring board and a manufacturing method of a wiring board.
2. Description of the Related Art
In recent years, a printed electronics technique is used to form a conductive layer on a top surface of a support member of a wiring board, which is generally used in semiconductor devices and electronic circuits. The printed electronics technique is to form a conductive layer pattern by printing a functional ink or paste, which is typically metal fine particles, directly on a base material. There are suggested wiring boards using various printing methods.
Japanese Laid-Open Patent Applications No. 2006-163418 and No. 2009-105413 disclose a wiring board having a conductive layer formed on a support member or the like so as to be capable of forming a thin-film transistor. A concave portion is formed on a support board by a laser abrasion method or etching method. The conductive layer is formed by applying a conductive material in the concave portion.
Japanese Laid-Open Patent Application No. 2013-016773 discloses a wiring board having a conductive layer formed in a concave portion on a top surface of a support member. The concave portion is formed in a variable wettability layer, of which a critical surface tension is changed by giving energy, on the top surface of the support member by using a layer abrasion method. The conductive layer is formed by applying conductive ink to the concave portion.
In order to form the conductive layer in the above-mentioned wiring board, the concave portion is first formed on the support board (including the variable wettability layer) by a laser abrasion method or etching method, and, then, a conductive material is applied to an interior of the concave portion. The shape of the concave portion varies in its size and width. However, as illustrated in a conceptual diagram of FIG. 1, the concave portion 90, in which the conductive layer 91 is formed, has a square-shape or trapezoid-shape having angled portions K.
Accordingly, electric field concentration tends to occur at the angled portions K, which may result in a decrease in a dielectric voltage between adjacent wirings. Additionally, when a lamination structure is formed, it may cause a decrease in an interlayer withstand voltage.